`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: HITSZ
// Engineer: 
// 
// Create Date: 2023/11
// Design Name: 
// Module Name: 
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    input wire        clk,
    input wire        rst,
    input wire        rx,
    output reg [15:0] led,
    output reg [7:0] led0_seg = 8'h0,
    output reg [7:0] led1_seg = 8'h0,
    output reg [7:0] led_bit = 8'h1,
    output wire       tx
);

wire [15:0]  switch;
wire [4:0]   button;
wire [7:0]   seg_seg = led_bit[3:0] == 4'h0 ? led1_seg : led0_seg;
reg [31:0] cnt = 0;
localparam integer ms2 = 200000;
remote_fpga_0 remote_fpga_0(
    .clk(clk),
    .rst(rst),
    .rx(rx),
    .switch(switch),
    .button(button),
    .seg_segment(seg_seg),
    .seg_bit(led_bit),
    .tx(tx),
    .led(led)
);

// test
always @ (posedge clk) begin
    led <= switch;
end

always @ (posedge clk) begin
    if (cnt == ms2) begin
        cnt <= 0;
        led_bit <= {led_bit[6:0], led_bit[7]};
    end
    else if (cnt < ms2) begin
        cnt <= cnt + 1;
    end
end

always @ (posedge clk) begin
    case (led_bit)
        8'h01: begin
            led0_seg <= 8'h80;
        end
        8'h02: begin
            led0_seg <= 8'hc0;
        end
        8'h04: begin
            led0_seg <= 8'he0;
        end
        8'h08: begin
            led0_seg <= 8'hf0;
        end
        8'h10: begin
            led1_seg <= 8'hf8;
        end
        8'h20: begin
            led1_seg <= 8'hfc;
        end
        8'h40: begin
            led1_seg <= 8'hfe;
        end
        8'h80: begin
            led1_seg <= 8'hff;
        end
        default: begin
            led0_seg <= 8'hff;
        end
    endcase
end
endmodule
